View MC9S08SF4CTJ_4870002.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

freescale semiconductor data sheet: technical data document number: mc9s08sf4 rev. 2, 4/2009 ? freescale semiconductor, inc., 2009. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. mc9s08sf4 20-pin tssop case 948e 16-pin tssop case 948f features ? 8-bit s08 central processor unit (cpu) ? up to 40 mhz cpu at 2.7 v to 5.5 v across temperature range of ?40 c to 125 c ? hc08 instruction set with added bgnd instruction ? support for up to 32 interrupt/reset sources ?on-chip memory ? 4 kb flash read/program/erase over full operating voltage and temperature ? 128-byte random-access memory (ram) ? security circuitry to prev ent unauthorized access to ram and flash contents ? power-saving modes ? two low power stop modes; reduced power wait mode ? allows clocks to remain en abled to specific peripherals in stop3 mode ? clock source options ? internal clock source (ics ) ? internal clock source module containing a frequency-locked-loop (fll) controlled by internal or ex ternal reference; precision trimming of internal reference allows 0.2% resolution and 1% deviation over 0?70 c and voltage, 2% deviation over ?40?85 c and voltage, or 3% deviation over ?40?125 c and voltage; supporting bus frequencies up to 20 mhz ? system protection ? watchdog computer operating properly (cop) reset with option to run from dedicated 1 khz internal clock source or bus clock ? low-voltage detection with reset or interrupt; selectable trip points ? illegal opcode detection with reset ? illegal address detection with reset ? flash block protection ? development support ? single-wire background debug interface ? breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints) ? on-chip in-circuit emulator (ice) debug module containing two comparators and nine trigger modes ? peripherals ? ipc ? prioritize interrupt sources besides inherent cpu interrupt table; support up to 32 interrupt sources and up to 4-level preemptive interrupt nesting ? adc ? 8-channel, 10-bit resolution; 2.5 s conversion time; automatic compare func tion; temperature sensor; internal bandgap reference ch annel; operation in stop; fully functional from 2.7 v to 5.5 v ? tpm ? one 40 mhz 6-channel and one 40 mhz 1-channel timer/pulse-width modulators (tpm) modules; selectable input cap ture, output compare, or buffered edge- or center-aligned pwm on each channel ? mtim16 ? two 16-bit modulo timers ? pwt ? two 16-bit pulse width timers (pwt); selectable driving clock, positive/negative/period capture ? pracmp ? two programmable reference analog comparators with eight optional inputs for both positive and negative inputs; 32-level internal reference voltages scaled by selectable reference inputs ? iic ? inter-integrated circuit bus module capable of operation up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; broadcast mode; 10-bit addressing ? kbi ? 4-pin keyboard interrupt module with software selectable polarity on edge or edge/level modes ? fds ? shut down output pin upon fault detection; the fault sources can be optional enabled separately; the output pin can be configured as output 1,0 and high impedance when a fault occurs based on module configuration ? input/output ? 18 gpios including one input-only pin and one output-only pin ? hysteresis and configurable pullup device on all input pins; schmitt trigger on pwt input pins; configurable slew rate and drive strength on all output pins. ? package options ? 16-pin tssop ? 20-pin tssop mc9s08sf4 series
mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 2 revision history the following revision history table summariz es changes contained in this document. revision date description of changes 2 4/30/2009 initial public release. related documentation reference manual (mc9s08sf4rm) contains extensive product information including modes of operation, memory, resets and interrupts, regist er definition, port pins, cpu, and all module information. 1 mcu block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 parameter classification . . . . . . . . . . . . . . . . . . . 5 3.3 absolute maximum ratings. . . . . . . . . . . . . . . . . 5 3.4 thermal characteristics. . . . . . . . . . . . . . . . . . . . 6 3.5 esd protection and latch-up immunity . . . . . . . 7 3.6 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . 8 3.7 supply current characteristics . . . . . . . . . . . . . 14 3.8 ics characteristics . . . . . . . . . . . . . . . . . . . . . . 16 3.9 ac characteristics. . . . . . . . . . . . . . . . . . . . . . . 17 3.9.1 control timing . . . . . . . . . . . . . . . . . . . . . 18 3.9.2 timer/pwm (tpm) module timing . . . . . 19 3.10 adc characteristics . . . . . . . . . . . . . . . . . . . . . 20 3.11 pracmp characteristics . . . . . . . . . . . . . . . . . .21 3.12 flash specifications . . . . . . . . . . . . . . . . . . . . . .22 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . .23 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.1 mechanical drawings . . . . . . . . . . . . . . . . . . . . .23 table of contents
mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 3 1 mcu block diagram the block diagram, figure 1 , shows the structure of the mc9s08sf4 mcu. figure 1. mc9s08sf4 series block diagram 2 pin assignments this section shows the pin assignments for the mc9s08sf4 series devices. user flash user ram hcs08 core cpu bdc 6-ch timer/pwm module ( tpm1 ) hcs08 system control resets and interrupts modes of operation power management voltage regulator port a 40 mhz internal clock source ( ics ) analog-to-digital converter( adc ) 8-ch 10-bit cop wakeup lv d 1-ch timer/pwm module ( tpm2 ) adp[5:0] v dd v ss 128 bytes 4096 bytes reset irq 16-bit modulo timer ( mtim16-2 ) 16-bit modulo timer ( mtim16-1 ) pulse width timer ( pwt1 ) pulse width timer ( pwt2 ) adp[6:7] pwti1 pwti2 pta0/kbi0/tclk/irq pta1/kbi1/reset pta2/kbi2/tpm1c0/fdsout0 pta3/kbi3/tpm1c1/fdsout1 pta4/tpm1c2/fdsout2 pta5/tpm1c3/fdsout3 pta6/tpm1c4/fdsout4 pta7/tpm1c5/fdsout5 tpm1c[5:0] irq port b ptb0/tpm2c0/fdsout6 ptb1/pwti1/adc0 ptb2/pwti2/adc1 ptb3/acmp3/adc2 ptb4/acmp2/adc3 ptb5/acmp1/adc4 ptb6/acmp0/adc5 ptb7/bkgd/ms tpm2c0 analog comparator ( pracmp2 ) analog comparator ( pracmp1 ) scl sda port c 4-pin keyboard ( kbi ) kbi[3:0] ptc0/adc6/scl ptc1/adc7/sda inter-intergrated ( iic ) interrupt priority ( ipc ) fault detection ( fds ) = not available in 16-pin tssop package debug module ( dbg ) acmp3 acmp2 acmp1 acmp0 fdsout[6:0] tclk tclk tclk tclk tclk tclk acmp3 acmp2 acmp1 acmp0 controller interrupt & shutdown circuit
mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 4 figure 2. mc9s08sf4 in 20-pin tssop package figure 3. mc9s08sf4 in 16-pin tssop package v dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pta0/kbi0/tclk/irq pta1/kbi1/reset pta2/kbi2/tpm1c0/fdsout0 pta3/kbi3/tpm1c1/fdsout1 pta4/tpm1c2/fdsout2 pta5/tpm1c3/fdsout3 pta6/tpm1c4/fdsout4 pta7/tpm1c5/fdsout5 ptb0/tpm2c0/fdsout6 v ss ptc1/sda/adc7 ptc0/scl/adc6 ptb7/bkgd/ms ptb6/acmp0/adc5 ptb5/acmp1/adc4 ptb4/acmp2/adc3 ptb3/acmp3/adc2 ptb2/pwti2/adc1 ptb1/pwti1/adc0 v dd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pta0/kbi0/tclk/irq pta1/kbi1/reset pta2/kbi2/tpm1c0/fdsout0 pta3/kbi3/tpm1c1/fdsout1 pta4/tpm1c2/fdsout2 pta5/tpm1c3/fdsout3 ptb0/tpm2c0/fdsout6 v ss ptb7/bkgd/ms ptb6/acmp0/adc5 ptb5/acmp1/adc4 ptb4/acmp2/adc3 ptb3/acmp3/adc2 ptb2/pwti2/adc1 ptb1/pwti1/adc0
introduction mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 5 3 electrical characteristics 3.1 introduction this section contains electrical a nd timing specifications for the mc9s 08sf4 series of microcontrollers available at the time of publication. 3.2 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a better understanding the following classi fication is used and the parameters are tagged accordingly in the tabl es where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 3.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond th e limits specified in table 2 may affect device reliability or cause permanent damage to the device. for functiona l operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appr opriate logic volta ge level (for instance, either v ss or v dd ) or the programmable pullup resistor associated with the pin is enabled. table 1. parameter classifications p those parameters are guaranteed during produ ction testing on each individual device. c those parameters are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations.
mc9s08sf4 series mcu data sheet, rev. 2 thermal characteristics freescale semiconductor 6 3.4 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage re gulator circuits and it is user-determined rather than being controlled by the mcu design. in order to take p i/o into account in power calculations , determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (h eavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. 1 where: table 2. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to 5.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value s pecified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma storage temperature range t stg ?55 to 150 c table 3. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h ?40 to 125 c thermal resistance (single-layer board) 20-pin tssop 16-pin tssop ja 115 123 c/w thermal resistance (four-layer board) 20-pin tssop 16-pin tssop ja 76 75 c/w
esd protection and latch-up immunity mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 7 t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglecte d. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. 2 solving equation 1 and equation 2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. 3 where k is a constant pertaining to the pa rticular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 3.5 esd protection and latch-up immunity although damage from electrostatic di scharge (esd) is much less comm on on these devices than on early cmos circuits, normal handling preca utions should be used to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can with stand exposure to reasonable levels of static without suffer ing any permanent damage. during the device qualification es d stresses were performed for the human body model (hbm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametr ic and functional testing is perf ormed per the applicable device specification at room temperature followed by hot te mperature, unless specified otherwise in the device specification.
mc9s08sf4 series mcu data sheet, rev. 2 dc characteristics freescale semiconductor 8 3.6 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table 4. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulses per pin ? 1 latch-up minimum input voltage limit ? ?2.5 v maximum input voltage limit ? 7.5 v table 5. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 2000 ? v 2 charge device model (cdm) v cdm 500 ? v 3 latch-up current at t a = 125 ci lat 100 ? ma table 6. dc characteristics (temperature range = ?40 to 125 c ambient) num c parameter symbol min typical max unit 1 p supply voltage (run, wait, and stop modes.) v dd 2.7 ? 5.5 v 2 p low-voltage detection threshold ? high range (v dd falling) (v dd rising) v lv d h 3.9 4.0 ? ? 4.1 4.2 v v p low-voltage detection threshold ? low range (v dd falling) (v dd rising) v lv d l 2.48 2.54 2.56 2.62 2.64 2.7 v v 3 p low-voltage warning threshold ? high range (v dd falling) (v dd rising) v lv w h 2.66 2.72 ? ? 2.82 2.88 v v p low-voltage warning threshold ? low range (v dd falling) (v dd rising) v lv w l 2.84 2.90 ? ? 3.00 3.06 v v 4d low-voltage inhibit reset/recover hysteresis 5 v 3 v v hys ? ? 100 60 ? ? mv mv 5p bandgap voltage reference factory trimmed at v dd = 3.0 v, temp = 25 cv bg 1.185 1.200 1.215 v 6p input high voltage (2.7 v v dd 5.5 v) (all digital inputs) v ih 0.65 v dd ?v dd + 0.3 v 7p input low voltage (2.7 v v dd 5.5 v) (all digital inputs) v il v ss ? 0.3 ? 0.35 v dd v
dc characteristics mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 9 8 d input hysteresis (all digital inputs) v hys 0.06 v dd ?0.30 v dd v 9p input leakage current (pins in high ohmic input mode) 1 v in = v dd5 or v ss5 i in ?1 ? 1 a 10 p internal pullup resistors 2 r pu 17.5 40.0 52.5 k p internal pulldown resistor (irq) r pd 12.5 ? 62.5 k 11 c output high voltage all i/o pins, low-drive strength, 5 v, i load = ?4 ma v oh v dd ? 1.5 ? ? v p output high voltage all i/o pins, low-drive strength, 5 v, i load = ?2 ma v dd ? 0.8 ? ? v c output high voltage all i/o pins, low-drive strength, 3 v, i load = ?1 ma v dd ? 0.8 ?? v c output high voltage all i/o pins, high-drive strength, 5 v, i load = ?15 ma v dd ? 1.5 ?? v p output high voltage all i/o pins, high-drive strength, 5 v, i load = ?10 ma v dd ? 0.8 ?? v c output high voltage all i/o pins, high-drive strength, 3 v, i load = ?5 ma v dd ? 0.8 ?? v 12 c output low voltage all i/o pins, low-drive strength, 5 v, i load = 4 ma v ol ?? 1.5 v p output low voltage all i/o pins, low-drive strength, 5 v, i load = 2 ma ?? 0.8 v c output low voltage all i/o pins, low-drive strength, 3 v, i load = 1 ma ?? 0.8 v c output low voltage all i/o pins, high-drive strength, 5 v, i load = 15 ma ?? 1.5 v p output low voltage all i/o pins, high-drive strength, 5 v, i load = 10 ma ?? 0.8 v c output low voltage all i/o pins, high-drive strength, 3 v, i load = 5 ma ?? 0.8 v 13 d maximum total i oh for all port pins 5 v 3 v |i oht | ? ? ? ? 100 60 ma d maximum total i ol for all port pins 5 v 3 v |i olt | ? ? ? ? 100 60 ma 14 d dc injection current 2, 3, 4, 5 v in < v ss , v in > v dd single pin limit total mcu limit, includes sum of all stressed pins |i ic | ? ? ? ? 0.2 5 ma ma 15 d input capacitance (all non-supply pins) c in ?? 7pf 1 maximum leakage current occurs at maximum operating temperat ure. current decreases by approximately one-half for each 8 c to 12 c in the temperature range from 50 c to 125 c. table 6. dc characteristics (continued)(temperature range = ?40 to 125 c ambient) (continued) num c parameter symbol min typical max unit
mc9s08sf4 series mcu data sheet, rev. 2 dc characteristics freescale semiconductor 10 figure 4. typical low-side driver (sink) characteristics low drive (ptxdsn = 0), v dd = 5.0 v, v ol vs. i ol 2 measurement condition for pull resistors: v in = v ss for pullup and v in = v dd for pulldown. 3 all functional non-supply pins are internally clamped to v ss and v dd . 4 input must be current limited to the value specified. to determine the value of the required current -limiting resistor, calcula te resistance values for positive and negative clamp vo ltages, then use the larger of the two values. 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consumi ng power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). typical low-side driver (lds) characteristics v dd = 5 v, porta, v ol vs i ol 0 1 2 3 4 5 6 1234567891011121314 i ol (ma) v ol (v) t=-40c t= 0c t=25c t=85c t=105c t=125c
dc characteristics mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 11 figure 5. typical low-side driver (sink) characteristics low drive (ptxdsn = 0), v dd = 3.0 v, v ol vs. i ol figure 6. typical low-side driver (sink) characteristics high drive (ptxdsn = 1), v dd = 5.0 v, v ol vs. i ol typical low-side driver (lds) characteristics v dd = 3 v, porta, v ol vs i ol 0 0.5 1 1.5 2 2.5 3 3.5 12345 i ol (ma) v ol (v) t=-40c t=0c t=25c t=85c t=105c t=125c typical low-side driver (hds) characteristics v dd = 5 v, porta, v ol vs i ol 0.00 0.20 0.40 0.60 0.80 1.00 1.20 12 34567 891011121314151617181920 i ol (ma) v ol (v) t=-40c t=0c t=25c t=85c t=105c t=125c
mc9s08sf4 series mcu data sheet, rev. 2 dc characteristics freescale semiconductor 12 figure 7. typical low-side driver (sink) characteristics high drive (ptxdsn = 1), v dd = 3.0 v, v ol vs. i ol figure 8. typical high-side driver (source) characteristics low drive (ptxdsn = 0), v dd = 5.0 v, v oh vs. i oh typical low-side driver (hds) characteristics v dd = 3 v, porta, v ol vs i ol 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 12345678910111213 i ol (ma) v ol (v) t=-40c t= 0c t=25c t=85c t= 85 t=125c typical high-side driver (lds) characteristics v dd = 5 v, porta, v oh vs i oh 0.00 1.00 2.00 3.00 4.00 5.00 6.00 0 -1-2-3-4-5-6-7-8-9 i oh (ma) v oh (v) t= -40c t= 0c t=25c t=85c t=105c t=125c
dc characteristics mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 13 figure 9. typical high-side driver (source) characteristics low drive (ptxdsn = 0), v dd = 3.0 v, v oh vs. i oh figure 10. typical high-side driver (source) characteristics high drive (ptxdsn = 1), v dd = 5.0 v, v oh vs. i oh typical high-side driver (lds) characteristics v dd = 3 v, porta, v oh vs i oh 0 0.5 1 1.5 2 2.5 3 3.5 0 -1-2-3 i oh (ma) v oh (v) t=-40c t=0c t=25c t=85c t=105c t=125c typical high-side driver (hds) characteristics v dd = 5 v, porta, v oh vs i oh 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 5.20 0 -1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20 i oh (ma) v oh (v) t=-40c t=0c t=25c t=85c t=105c t=125c
mc9s08sf4 series mcu data sheet, rev. 2 supply current characteristics freescale semiconductor 14 figure 11. typical high-side driver (source) characteristics high drive (ptxdsn = 1), v dd = 3.0 v, v oh vs. i oh 3.7 supply current characteristics this section includes information about power supply current in various operating modes. table 7. supply current characteristics num c parameter symbol v dd (v) typical 1 max 2 unit 1 p run supply current 3 measured at (cpu clock = 2 mhz, f bus = 1 mhz) ri dd 5 1.75 1.77 ma d 3 1.71 1.73 2 p run supply current 3 measured at (cpu clock = 16 mhz, f bus = 8 mhz) ri dd 5 5.69 6.25 ma d 3 4.63 4.66 3 p run mode supply current 3 measured at (cpu clock = 40 mhz, f bus = 20 mhz) ri dd 5 11.53 12.00 ma d 3 10.39 11.00 4 p wait mode supply current 4 measured at (f bus = 8 mhz) wi dd 5 3.95 4.54 ma d 3 3.58 4.00 5 p wait mode supply current 4 measured at ( f bus = 20 mhz) wi dd 5 8.36 9.62 ma d 3 7.97 8.07 6 p stop2 mode supply current ?40 to 85 c ?40 to 125 c ?40 to 85 c ?40 to 125 c s2i dd 51.99 18.47 a p 100 d 31.95 16.9 d 90 typical high-side driver (hds) characteristics v dd = 3 v, porta, v oh vs i oh 0 0.5 1 1.5 2 2.5 3 3.5 0 -1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 i oh (ma) v oh (v) t=-40c t= 0c t=25c t=85c t=105c t=125c
supply current characteristics mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 15 7 p stop3 mode supply current ?40 to 85 c ?40 to 125 c ?40 to 85 c ?40 to 125 c s3i dd 52 18.4 a p 100 d 31.97 16.82 d 90 8 d pracmp (prg disabled) adder to stop3, 25 c ? 5 28.87 ? na d 3 27.06 ? na 9 d pracmp (prg enabled) adder to stop3, 25 c ? 5 79.42 ? na d357.4?na 10 d adc adder to stop2 or stop3, 25 c? 525?na d36?na 11 d lvd adder to stop3 (lvde = lvdse = 1) ? 5 83.52 ? na d 3 83.52 ? na 12 d adder to stop3 for oscillator enabled (irefsten = 1) ? 50.03? a d 3 0.01 ? a 13 d tpm1 and tpm2 adder to run mode, 25 c (cpu clock = 40 mhz, f bus = 20 mhz) ? 50.16?ma d 3 0.18 ? ma 14 d pwt1 and pwt2 adder to run mode, 25 c (cpu clock = 40 mhz, f bus = 20 mhz) ? 50.43?ma d 3 0.41 ? ma 15 d pracmp adder to run mode, 25 c (cpu clock = 40 mhz, f bus = 20 mhz) ? 50.35?ma d 3 0.35 ? ma 16 d mtim1 and mtim2 adder to run mode, 25 c (cpu clock = 40 mhz, f bus = 20 mhz) ? 50.26?ma d 3 0.24 ? ma 17 d adc adder to run mode, 25 c (cpu clock = 40 mhz, f bus = 20 mhz) ? 50.42?ma d 3 0.32 ? ma 18 d iic adder to run mode, 25 c (cpu clock = 40 mhz, f bus = 20 mhz) ? 50.56?ma d 3 0.53 ? ma 1 typicals are measured at 25 c. 2 values given here are preliminary estimates prior to completing characterization. 3 all modules except adc active, and does not include any dc loads on port pins. 4 most customers are expected to find that the auto-wakeup from a stop mode can be used instead of the higher current wait mode. table 7. supply current characteristics (continued) num c parameter symbol v dd (v) typical 1 max 2 unit
mc9s08sf4 series mcu data sheet, rev. 2 ics characteristics freescale semiconductor 16 figure 12. typical run i dd vs. bus freq. (fei) (adc off) 3.8 ics characteristics refer to figure 13 for crystal or resonator circuits. table 8. ics specifications (temperature range = ?40 to 125 c ambient ) num c characteristic symbol min typical 1 max unit 1 t internal reference start-up time t irst ?60100 s 2 p average internal reference frequency ? trimmed f int_t ? 39.0625 ? khz 3 p dco output frequency range ? trimmed low range (drs = 00) f dco_t 16 ? 20 mhz p middle range (drs = 10) 32 ? 40 4p total deviation of dco output from trimmed frequency 2 over full voltage and temperature range of ?40 c to 125 c f dco_t ? ?1.0 to 0.5 3 %f dco 5d total deviation of dco output from trimmed frequency over full voltage and temperature range of ?40 c to 85 c ?1.0 to 0.5 2 6d total deviation of dco output from trimmed frequency over fixed voltage and temperature range of 0 to 70 c 0.5 1 7c fll acquisition time 2,3 t acquire ??1ms 8c long term jitter of dco output clock (averaged over 2 ms interval) 4 c jitter ?0.020.2 %f dco typical ri dd (v dd = 5 v, adc off) vs bus frequency 0.0000 2.0000 4.0000 6.0000 8.0000 10.0000 12.0000 14820 bus frequency ma t=-40c t=0c t=25c t=85c t=125c
ac characteristics mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 17 figure 13. deviation of dco output from trimmed frequency (20 mhz, 5.0 v) 3.9 ac characteristics this section describes ac timing char acteristics for each peripheral system. 1 data in typical column was characterized at 5.0 v, 25 c or is typical recommended value. 2 this parameter is characterized and not tested on each device. 3 this specification applies to any time the fll reference so urce or reference divider is changed, trim value changed, dmx32 bit is changed, drs bit is changed, or changing fr om fll disabled (fbelp, fbilp) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f bus . measurements are made with the device powe red by filtered supplies and clocked by a stable external clock signal. noise injected into th e fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. tbd -2.00% -1.50% -1.00% -0.50% 0.00% 0.50% 1.00% -60 -40 -20 0 20 40 60 80 100 120 temperature deviation (%)
mc9s08sf4 series mcu data sheet, rev. 2 ac characteristics freescale semiconductor 18 3.9.1 control timing figure 14. reset timing figure 15. irq/kbipx timing table 9. control timing parameter symbol min typical 1 1 data in typical column was characterized at 5.0 v, 25 c. max unit bus frequency (t cyc = 1/f bus )f bus 1?20mhz external reset pulse width 2 2 this is the shortest pulse that is guaranteed to be recognized. t extrst 100 ? ? ns irq pulse width asynchronous path 2 synchronous path 3 3 this is the minimum pulse width that is guaranteed to pass th rough the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. t ilih, t ihil 100 1.5 t cyc ??ns kbipx pulse width asynchronous path 2 synchronous path 3 t ilih, t ihil 100 1.5 t cyc ??ns port rise and fall time (load = 50 pf) 4 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 125 c. t rise , t fall ? ? 3 30 ? ? ns bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ? ? ns bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 5 5 to enter bdm mode following a por, bkgd/ms should be held low during the power-up and for a hold time of t msh after v dd rises above v lv d . t msh 100 ? ? s t extrst reset pin t ihil irq/kbipx t ilih irq/kbipx
ac characteristics mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 19 3.9.2 timer/pwm (tpm) module timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. figure 16. timer external clock figure 17. timer input capture pulse table 10. tpm/mtim input timing function symbol min max unit external clock frequency f tclk dc f timer /4 mhz external clock period t tclk 4?t cyc external clock high time t clkh 1.5 ? t cyc external clock low time t clkl 1.5 ? t cyc input capture pulse width for tpm t icpw 1.5 ? t cyc timer clock frequency f timer ?40mhz t text t clkh t clkl tclk t icpw tpmchn t icpw tpmchn
mc9s08sf4 series mcu data sheet, rev. 2 adc characteristics freescale semiconductor 20 3.10 adc characteristics table 11. adc characteristics num c characteristic cond itions symb min typical 1 max unit comment 1 d supply current adlpc = 1 adlsmp = 1 adco = 1 v dda 3.6 v (3.0 v typ) i dda ? 110 ? a over temperature (typ 25 c) d v dda 5.5 v (5.0 v typ) ? 130 ? 2 d supply current adlpc = 1 adlsmp = 0 adco = 1 v dda 3.6 v (3.0 v typ) i dda ? 200 ? a d v dda 5.5 v (5.0 v typ) ? 220 ? 3 d supply current adlpc = 0 adlsmp = 1 adco = 1 v dda 3.6 v (3.0 v typ) i dda ? 320 ? a d v dda 5.5 v (5.0 v typ) ? 360 ? 4 d supply current adlpc = 0 adlsmp = 0 adco = 1 v dda 3.6v (3.0 v typ) i dda ? 580 ? a d v dda 5.5v (5.0 v typ) ? 660 ? 5 d supply current stop, reset, module off i dda ? <1 100 na 6 d ref voltage high ? v refh 2.7 v dda v dda v d ref coltage low ? v refl v ssa v ssa v ssa v 7 d adc conversion clock high speed (adlpc = 0) f adck 0.4 ? 8.0 mhz t adck = 1/f adck d low power (adlpc = 1) 0.4 ? 4.0 8 d adc asynchronous clock source high speed (adlpc = 0) f adack 2.546.6 mhz t adack = 1/f adack d low power (adlpc = 1) 1.25 2 3.3 9 d conversion time short sample (adlsmp = 0) t adc 20 20 23 t adck cycles add 2 to 5 t bus =1/f bus cycles d long sample (adlsmp = 1) 40 40 43 10 d sample time short sample (adlsmp = 0) t ads 444 t adck cycles d long sample (adlsmp = 1) 24 24 24 11 d input voltage ? v adin v refl ?v refh v 12 d input capacitance ?c adin ? 7 10 pf not tested 13 d input impedance ? r adin ?515k not tested 14 d analog source impedance ?r as ??10 2 k external to mcu
pracmp characteristics mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 21 3.11 pracmp characteristics 15 d ideal resolution (1 lsb ) 10-bit mode res 2.637 4.883 5.371 mv v refh /2 n d 8-bit mode 10.547 19.53 21.48 16 d total unadjusted error 10-bit mode e tue 0 1.5 3.5 lsb includes quantization d8-bit mode 0 0.7 1.0 17 p differential non-linearity 3 10-bit mode dnl 0 0.5 1.0 lsb c8-bit mode 0 0.3 0.5 18 p integral non-linearity 10-bit mode inl 0 0.5 1.0 lsb c8-bit mode 0 0.3 0.5 19 d zero-scale error 10-bit mode e zs 0 1.5 3.1 lsb v adin = v ssa d8-bit mode 0 0.5 0.7 20 d full-scale error 10-bit mode e fs 0 1.0 1.5 lsb v adin = v dda d8-bit mode 0 0.5 0.5 21 d quantization error 10-bit mode e q ?? 0.5 lsb 8-bit mode is not truncated 22 p temp sensor slope ?40?25 c??3.266?? 25?125 c??3.638?? 23 p temp sensor voltage ???1.396?? 1 typical values assume v dda = 5.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 at 4 mhz, for maximum frequency, use proportionally lower source impedance. 3 monotonicity and no-missing-codes guaranteed table 12. pracmp specifications num c characteristic symbol min typical max unit 1 p supply voltage v pwr 2.70 ? 5.50 v 2 c supply current (active) (prg enabled) i ddact1 ??60 a 3 c supply current (active) (prg disabled) i ddact2 ??40 a 4 c supply current (acmp and prg all disabled) i dddis ?? 2 na 5 c analog input voltage v ain v ss ? 0.3 ? v dd50 v 6 c analog input offset voltage v aio ?540mv 7 c analog comparator hysteresis v h 3.0 ? 20.0 mv 8 c analog input leakage current i alkg ?? 1 na 9 c analog comparator initialization delay t ainit ??1.0 s table 11. adc characteristics (continued) num c characteristic cond itions symb min typical 1 max unit comment
mc9s08sf4 series mcu data sheet, rev. 2 flash specifications freescale semiconductor 22 3.12 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power s ources other than the normal v dd supply. for more detailed information about progra m/erase operations, see the memory section. 10 d programmable reference generator inputs v in1 (v dd50 ) 2.7 5.0 5.5 v 11 d programmable reference generator inputs v in2 (v dd25 ) 2.25 2.5 2.75 v 12 c programmable reference generator step size v step ?0.25 0 0.25 lsb 13 p programmable reference generator voltage range v prgout v in /32 ? v in v table 13. flash characteristics characteristic symbol min typical max unit supply voltage for program/erase ?40 c to 125 c v prog/erase 2.7 ? 5.5 v supply voltage for read operation v read 2.7 ? 5.5 v internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 ? 200 khz internal fclk period (1/fclk) t fcyc 5 ? 6.67 s byte program time (random location) (2) t prog 9t fcyc byte program time (burst mode) (2) t burst 4t fcyc page erase time 2 2 these values are hardware state machine c ontrolled. user code does not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc mass erase time (2) t mass 20,000 t fcyc program/erase endurance 3 t l to t h = ?40 c to 125 c t = 25 c 3 typical endurance for flash was evaluated for this product family on the 9s12dx64. for additional information on how delta defines typical endurance, please refer to engineering bulletin eb619/d, typical endurance for nonvolatile memory . 10,000 ? ? 100,000 ? ? cycles data retention 4 4 typical data retention values are based on intrinsic capability of the te chnology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how delta defines typical data retention, please refer to engineering bulletin eb618/d, typical data retention for nonvolatile memory. t d_ret 15 100 ? years table 12. pracmp specifications (continued) num c characteristic symbol min typical max unit
mechanical drawings mc9s08sf4 series mcu data sheet, rev. 2 freescale semiconductor 23 4 ordering information this section contains ordering info rmation for device numbering system example of the device numbering system: 5 package information 5.1 mechanical drawings the following pages are me chanical drawings for th e packages described in table 14 . for the latest available drawings, please visit our web site ( http://www.freescale.com ) and enter the package?s document number into the keyword search box. table 14. package descriptions pin count package type abbreviation designator case no. document no. 20 thin shrink small outline package tssop tj 948e 98ash70169a 16 thin shrink small outline package tssop tg 948f 98ash70247a sf mc temperature range family memory status core (m= ?40 c to 125 c) (9 = flash-based) 9 s08 xx (mc = fully qualified) package designator (see ta b l e 1 4 ) approximate flash size in kbytes 4x (v = ?40 c to 105 c) (c = ?40 c to 85 c)

how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009. all rights reserved. mc9s08sf4 rev. 2 4/2009 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part.

▲Up To Search▲

Price & Availability of MC9S08SF4CTJ

	To Download MC9S08SF4CTJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .